1. Field of the Invention
The present invention relates to a symbol clock regenerating apparatus, program and method for regenerating a symbol clock by detecting a symbol timing for a digital modulation signal.
2. Related Background Art
Generally, in a receiver for receiving the digital modulation signal, when a process of regenerating a symbol clock from a baseband signal obtained by detecting a modulation signal and regenerating a digital signal based on the symbol clock is performed, the symbol timing is deviated due to influence of a deviation in the reference oscillation frequency between transmitter and receiver or fading. If this deviation is greater, the bit error rate is worse, disabling the regeneration of data. Thus, conventionally, the symbol timing is captured, and the symbol clock is corrected to follow the symbol timing synchronously.
FIG. 7 is a block diagram showing the configuration of a clock regenerating apparatus in the conventional example in which such synchronous follow-up is enabled. In this apparatus, the symbol timing is acquired based on a synchronization word included in the detection signal, and a voltage-controlled oscillator circuit (hereinafter referred to as a “VCO”) 91 is controlled to be synchronous with it to generate a symbol clock. At this time, the VCO 91 is controlled, based on an instantaneous value and a reference value obtained by the symbol clock, to correct the symbol clock. The detection signal is the instantaneous value of amplitude converted from a FSK (frequency-shift keying) modulation signal representing a four-value symbol.
In the same figure, reference numeral 92 designates a four-value determination part for generating the four-value signal based on the detection signal, 93 designates a clock delay part for delaying the symbol clock by a half period to output a delay clock, 94 designates a delay part for storing the value of detection signal at the timing when the delay clock rises, and outputting it, 95 designates a delay part for storing the output of the delay part 94 at the timing when the symbol clock rises, and outputting it, 96 designates a delay part for storing the four-value signal outputted by the four-value determination part 92 at the timing when the symbol clock rises, and outputting the symbol data, and 97 designates a delay part for storing the output of the delay part 96 at the timing when the symbol clock rises, and outputting it.
Also, reference numeral 98 designates an adder for adding the output of the delay part 97 and the symbol data, 99 designates an attenuation part for converting the output value of the adder 98 into its half value, 100 designates an adder for adding the outputs of the delay part 95 and the attenuation part 99, 101 designates an adder for adding the output of the attenuation part 99 and the symbol data, 102 designates an adder for adding the output of the delay part 97 and the symbol data, 103 designates a multiplier for multiplying the outputs of the adder 100 and the adder 101, 104 designates a gate part for passing the output of the multiplier 103 when the output value of the adder 102 is not zero and shutting off the output when it is zero, and 105 designates a low pass filter for controlling the VCO 91 based on the output of the gate part 104.
The low pass filter 105 counts up at a predetermined period while the output of the gate part 104 is positive, or counts down at the period while it is negative, supposing that the initial value is M. Thereby, if the count value reaches 2M, the VCO 91 is instructed to advance the phase of symbol clock by a prescribed value to reset the count value. Conversely, if the count value reaches zero, the VCO 91 is instructed to delay the phase of symbol clock by the prescribed value to reset the count value.
In this configuration, the VCO 91 is driven at the symbol timing acquired based on the synchronization word included in the detection signal to output the symbol clock. Meanwhile, the phase of symbol clock is corrected in the following way.
An intermediate value between the symbol data outputted by the delay part 96 and the preceding symbol data outputted by the delay part 97 is acquired by the adder 98 and the attenuation part 99, and defined as an expected value. On the other hand, a sample value of the detection signal corresponding to the intermediate value is acquired by the clock delay part 93, and the delay parts 94 and 95, and defined as a measured value. When the symbol clock has no deviation, a difference between the expected value and the measured value obtained by the adder 100 is ideally zero. When the symbol clock has a deviation, this difference is not zero, and the measured value is deviated to the plus or minus from the expected value.
Thus, the low pass filter 105 is controlled by the adders 101, 102, the multiplier 103 and the gate part 104 to count down when the phase of symbol clock advances, or count up when it delays. Thereby, the symbol clock is corrected so that if the count value reaches 2M, the phase is advanced, or if the count value reaches zero, the phase is delayed.
[Patent document 1] Japanese Patent Application Laid-Open No. 2003-333113